Western Digital Corp. announced a partnership with OÜ, in collaboration with SiFive, Inc
June 2019 by Marc Jacob
Western Digital Corp. announced a new a partnership with PlatformIO Labs, OÜ, in collaboration with SiFive, Inc., to extend the openness of PlatformIO vendor-agnostic embedded development platform to include new tools, thereby providing an end-to-end, open environment for innovation, including development for RISC-V. Fueled by positive feedback from the developer community, Western Digital also unveiled key new enhancements to its open-sourced RISC-V SweRV Core™ and cache-coherent fabric, OmniXtend™. Together, these announcements further the company’s support of the RISC-V initiative and extend its leadership in the development of new open, purpose-built compute architectures to address the explosive increase in data driven by high-growth applications such as artificial intelligence (AI), machine learning (ML), Internet of Things (IoT), and more.
PlatformIO enables the streamlined design of a wide range of embedded hardware and software technology, supporting numerous leading operating systems (OS) and development platforms, as well as hundreds of boards. Its unified project configuration capabilities leverage built-in package and library managers automatically install the required library and toolchains depending on a project build environment.
With support from strategic investments from Western Digital and SiFive, software programmers developing for RISC-V and other architectures can use now use PlatformIO’s previously paid PlatformIO Plus™ features at no cost, including the PIO Plus Unified Debugger and PIO Uniting Testing Engine tools, as well as remote access capabilities. Engineers can also replicate their project in multiple OS environments, thereby providing greater design flexibility, and eliminating the need to learn complex vendor-specific toolkits. With the openness of these unique, multi-architecture testing and debugging resources, PlatformIO is now a fully open-source supportive environment for end-to-end design of embedded technology, including those by the RISC-V ecosystem.
Western Digital is also accelerating RISC-V hardware design with an updated SweRV Core. Integrated into SweRV Core 1.1 are a wide range of improvements that notably enhance its performance and reliability. These include faster divide and fetch functions, the incorporation of I/O timing control, better error correction capabilities, multi-core debug improvements and more. The 32-bit, in-order core was designed for internal usage and open-sourced to the RISC-V ecosystem by Western Digital earlier this year. The updated core will be available for download today.
In addition, Western Digital’s OmniXtend memory-centric system architecture can now operate with Barefoot Network’s end-user P4-programmable Tofino™ Ethernet switch ASIC. OmniXtend, a new, open approach to providing cache coherent memory-over-an-Ethernet fabric, enables access to and data sharing with a wide variety of components. The compatibility with the Tofino switch ASIC is significant as it allows data center architects to implement innovative architectures where the main memory is central to the network. OmniXtend enables cache coherency to be equally shared with GPUs, FPGAs, machine-learning accelerators and CPUs. This can support further advancements in data center architectures, CPU micro-architecture and purpose-built compute acceleration in data-centric devices.
These announcements build-on Western Digital’s long-standing commitment to advancing the RISC-V ecosystem and driving data-centric innovation through open source collaboration, including multiple related strategic investments and partnerships, and demonstrated progress toward its stated goal of transitioning one billion of the company’s processor cores to the RISC-V architecture. RISC-V enables the company to participate in and leverage a broad community of inventors focused on bringing increasing amounts of processing power closer to data. With compute power closer to data, customers can minimize data movement at the edge and within their data centers, optimizing processing that is based on location, workload or a time-value need.